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An 8-bit 160 MS/s folding-interpolating adc with optimizied active averaging/interpolating network

Azin, M ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2005.1466044
  3. Publisher: 2005
  4. Abstract:
  5. An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE
  6. Keywords:
  7. Circuit designs ; CMOS digital process ; High-speed ; Interpolating ADC ; Low Power ; Silicon area ; Supply voltages ; Multicarrier modulation ; Integrated circuit manufacture
  8. Source: IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 6150-6153 ; 02714310 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/1466044