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A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0. 18μm digital CMOS technology

Tajalli, A ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1109/ESSCIR.2005.1541592
  3. Publisher: 2005
  4. Abstract:
  5. This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045 μm2 silicon area. © 2005 IEEE
  6. Keywords:
  7. CMOS integrated circuits ; Data acquisition ; Digital devices ; Electric clocks ; Product design ; Signal receivers ; Clock and data recovery (CDR) ; Power dissipation ; Short haul receivers ; Oscillators (electronic)
  8. Source: ESSCIRC 2005: 31st European Solid-State Circuits Conference, Grenoble, 12 September 2005 through 16 September 2005 ; 2005 , Pages 193-196 ; 0780392051 (ISBN); 9780780392052 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1541592