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A compact, low power, fully integrated clock frequency doubler

Tajalli, A ; Sharif University of Technology | 2003

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  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2003.1301847
  3. Publisher: 2003
  4. Abstract:
  5. A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from the desired nominal value. © 2003 IEEE
  6. Keywords:
  7. Capacitors ; Sensitivity analysis ; Frequency doublers ; CMOS integrated circuits ; Capacitors ; Sensitivity analysis ; Frequency doublers ; CMOS integrated circuits ; Clocks
  8. Source: 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003, Sharjah, 14 December 2003 through 17 December 2003 ; Volume 2 , 2003 , Pages 563-566 ; 0780381637 (ISBN); 9780780381636 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1301847