Loading...

An RT-Level Low Power Design Technique for Digital Circuits Implemented on FPGAs

Kazemi Najafabadi, Mehdi | 2015

366 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 48564 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. RT-level techniques are one of the most important categories of techniques employed for decreasing power consumption in digital systems. These techniques are usually applied in the HDL description of the system, however some of them are applicable automatically by the synthesis tools. Some of the most commonly used RT-level techniques include Operand isolation, Clock gating, Concurrency & Redundancy, Pre-computation and Pipeline for low power. However these techniques have been mostly employed in ASIC designs, and FPGAs have scarcely been addressed. Application of these techniques on FPGAs might need special considerations, since resources on FPGAs are inherently different than their ASIC counterparts. As an example, clock gating could not be used as easily on FPGAs as on ASICs since clocking resources on FPGAs are limited and fixed. Also operand isolation needs latches as storage elements which are not found on FPGAs as pre-built elements and implementation of these elements on FPGAs might have implications on their performance (and even negatively on their power consumption). The aim of this research is to study the current RT-level techniques for decreasing power consumption used on ASICs and trying to extend them to be used on FPGAs. Another objective of the study is to propose new RT-level strategies and techniques for power reduction on FPGAs
  9. Keywords:
  10. Field Programmable Gate Array (FPGA) ; Energy Reduction ; Low-Power Design ; Energy Consumption ; Digital Design ; RT-Level Design

 Digital Object List

 Bookmark

No TOC