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Suppose that A is a large subset of N. It is interesting to think about the arithmetic progressions in A.In 1936, Erdos and Turan conjectured that for > 0 and k 2 N, there exists N = N(k; ) that for all subsets A {1; 2; : : : ;N}, if lAl N, A has a nontrivial arithmetic progression of length k. Roth proved the conjecture for k = 3 in 1953. In 1969, Szemeredi proved the case k = 4 and in 1975, he gave a combinatorial proof for the general case. In 1977, using ergodic theory, Furstenberg gave a different proof for the Erdos-Turan conjecture (or Szemeredi Theorem!) and finally Gowers found another proof for the Szemeredi theorem, which was an elegant generalization of the Roth’s proof for k =... 

In this dissertation, we study (first-order) arithmetical interpretations for propositional (modal and non-modal) logics. More precisely, the following results are included in this dissertation: an axiomatization for provability logic of Heyting Arithmetic, HA, and its self-completion HA := HA + PrHA(⌜A⌝) ! A for 1-substitutions is provided, and their arithmetical completeness theorems are proved. We also show that they are decidable. The de Jongh property for Basic Arithmetic BA, HA and HA + □ are proved  

Shrinking the dimensions of transistors in recent fabrication technologies has led to an increase in the aging rate of chips, as the most important challenge in reliability of new processors. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effect of transistor shrinkage. These two effects decrease the switching speed of transistors by increasing its threshold voltage over time. Threshold voltage shift causes timing violation in combinational parts of circuit and decreases the robustness of sequential parts against soft errors. Between different units of a processor, Arithmetic and Logic Unit (ALU) is one of the most susceptible units... 

Arithmetic circuits are considered as very important blocks of datapaths in microprocessor structures. Due to the high importance of these circuits, several optimization approaches in different levels of abstraction have been proposed for them. These approaches can be implemented by either software or manually by digital logic designers. As within this optimization process, specially, in manual approaches, the probability of introducing logic bugs in the circuit is high, it would then be necessary to make use of verification and debugging techniques for the designed circuits. One of the classic verification methods is simulation. This approach is not suitable for large designs and it does... 

Szemeredi's theorem is one of the significant theorems in additive combinatorics which was started by Van Der Waerden's theorem in 1927. Erdos and Turan conjectured generalized versions of Van Der Waerden's theorem in several ways included Szemeredi's theorem. In 1975 Szemeredi proved the conjecture using complicated combinatorial methods. In 1977 H. Furstenberg proved Szemeredi's theorem via the Ergodic theory approach which led to prove polynomial Szemeredi's theorem and multi-dimensional Szemeredi's theorem. The Ergodic approach is the only known approach so far to these generalizations of this theorem which is named Ergodic Ramsey theory and led to some other problems in Ergodic theory... 

Zero knowledge proofs allow a person (prover) to convince another person (verifier) that he has performed a specific computation on a secret data correctly, and has obtained a true answer, without having to disclose the secret data. QAP (Quadratic Arithmetic Program) based zkSNARKs (zero knowledge Succinct Non-interactive Argument of Knowledge) are a type of zero knowledge proof. They have several properties that make them attractive in practice, e.g. verifier's work is very easy. So they are used in many areas such as Blockchain and cloud computing. But yet prover's work in QAP based zkSNARKs is heavy, therefore, it may not be possible for a prover with limited processing resource to run... 

Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since... 

In mechanical products, individual components are placed together in an assembly to deliver a certain function. The performance, quality and cost of product, selection of manufacturing process, measurement and inspection techniques, and the assemblability of the product are significantly affected by part tolerances. The dimensional and geometrical tolerances of individual parts accumulate and affect the functional requirements on the final assembly. Tolerance analysis is a key analytical tool for estimation of accumulating effects of the individual part tolerances on the functional requirements of a mechanical assembly. This thesis presents a new feature based method to tolerance analysis... 

Redundant number systems provide for carry-free arithmetic, where the result of arithmetic operations is achieved, in redundant format, without the need for latent carry propagation. However conversion of the result to a conventional nonredundant representation, always, requires carry propagation. Therefore, efficient use of redundant number systems is feasible when a series of arithmetic operations is to be performed before the need arises to obtain the result in a nonredundant representation. Redundant number systems have been used in several special purpose integrated designs (e.g., DSP applications) and also as intermediate number representation in complex arithmetic operations... 

Provability Logic is the study of Peano Arithmetic from the point of provability. The ◻ of modal logic is interpreted as ”Provable in PA ”. Gödel’s technique of proof, in his incompleteness theorems, showed that meta-lingual sentences such as ”A is provable in PA ” can be expressed by sentences of object language. Studying provability in the system K4 will lead us to a soundness theorem but in 1976, Robert Solovay showed that if we add an axiom -known as Löb’s axiom- to the system K4, we will have a completeness theorem as well. So GL = K4 + Löb is the provability logic of PA. In this thesis we will study these theorems