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    Frameworks for the Exploration and Implementation of Generalized Carry-Free Redundant Number Systems

    , Ph.D. Dissertation Sharif University of Technology Jaberipur, Ghassem (Author) ; Ghodsi, Mohammad (Supervisor) ; Parhami, Behrooz (Supervisor)
    Abstract
    Redundant number systems provide for carry-free arithmetic, where the result of arithmetic operations is achieved, in redundant format, without the need for latent carry propagation. However conversion of the result to a conventional nonredundant representation, always, requires carry propagation. Therefore, efficient use of redundant number systems is feasible when a series of arithmetic operations is to be performed before the need arises to obtain the result in a nonredundant representation. Redundant number systems have been used in several special purpose integrated designs (e.g., DSP applications) and also as intermediate number representation in complex arithmetic operations... 

    Provability Logic

    , M.Sc. Thesis Sharif University of Technology Aboolian, Narbe (Author) ; Behrostaghi, Mohammad Ardeshir (Supervisor)
    Abstract
    Provability Logic is the study of Peano Arithmetic from the point of provability. The ◻ of modal logic is interpreted as ”Provable in PA ”. Gödel’s technique of proof, in his incompleteness theorems, showed that meta-lingual sentences such as ”A is provable in PA ” can be expressed by sentences of object language. Studying provability in the system K4 will lead us to a soundness theorem but in 1976, Robert Solovay showed that if we add an axiom -known as Löb’s axiom- to the system K4, we will have a completeness theorem as well. So GL = K4 + Löb is the provability logic of PA. In this thesis we will study these theorems  

    The ∑ 1-Provability Logic of Intuitionistic Arithmetic

    , Ph.D. Dissertation Sharif University of Technology Mojtahedi, Mojtaba (Author) ; Ardeshir, Mohammad (Supervisor)
    Abstract
    In this dissertation, we study (first-order) arithmetical interpretations for propositional (modal and non-modal) logics. More precisely, the following results are included in this dissertation: an axiomatization for provability logic of Heyting Arithmetic, HA, and its self-completion HA := HA + PrHA(⌜A⌝) ! A for 1-substitutions is provided, and their arithmetical completeness theorems are proved. We also show that they are decidable. The de Jongh property for Basic Arithmetic BA, HA and HA + □ are proved  

    Tolerance Analysis of Mechanical Assemblies Based on Fuzzy Logic and Modal Interval Arithmetic

    , Ph.D. Dissertation Sharif University of Technology Khodaygan, Saeed (Author) ; Movahhedy, Mohammad Reza (Supervisor) ; Saadat Foumani, Mahmoud (Supervisor)
    Abstract
    In mechanical products, individual components are placed together in an assembly to deliver a certain function. The performance, quality and cost of product, selection of manufacturing process, measurement and inspection techniques, and the assemblability of the product are significantly affected by part tolerances. The dimensional and geometrical tolerances of individual parts accumulate and affect the functional requirements on the final assembly. Tolerance analysis is a key analytical tool for estimation of accumulating effects of the individual part tolerances on the functional requirements of a mechanical assembly. This thesis presents a new feature based method to tolerance analysis... 

    On The Existence of Arithmetic Progressions In Subsets of Integers

    , M.Sc. Thesis Sharif University of Technology Malekian, Reihaneh (Author) ; Alishahi, Kasra (Supervisor) ; Hatami, Omid (Supervisor)
    Abstract
    Suppose that A is a large subset of N. It is interesting to think about the arithmetic progressions in A.In 1936, Erdos and Turan conjectured that for > 0 and k 2 N, there exists N = N(k; ) that for all subsets A {1; 2; : : : ;N}, if lAl N, A has a nontrivial arithmetic progression of length k. Roth proved the conjecture for k = 3 in 1953. In 1969, Szemeredi proved the case k = 4 and in 1975, he gave a combinatorial proof for the general case. In 1977, using ergodic theory, Furstenberg gave a different proof for the Erdos-Turan conjecture (or Szemeredi Theorem!) and finally Gowers found another proof for the Szemeredi theorem, which was an elegant generalization of the Roth’s proof for k =... 

    Designing a 32-Bit Fault-Tolerant ALU Using EDAC

    , M.Sc. Thesis Sharif University of Technology (Author) ; Vosughi Vahdat, Bijan (Supervisor) ; Mortazavi, Mohammad (Supervisor)
    Abstract

    Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since... 

    Optimization and Verification of Arithmetic Circuits under Different Levels of Abstraction

    , M.Sc. Thesis Sharif University of Technology Sarbishei, Omid (Author) ; Tabandeh, Mahmoud (Supervisor) ; Alizadeh, Bijan (Supervisor)
    Abstract
    Arithmetic circuits are considered as very important blocks of datapaths in microprocessor structures. Due to the high importance of these circuits, several optimization approaches in different levels of abstraction have been proposed for them. These approaches can be implemented by either software or manually by digital logic designers. As within this optimization process, specially, in manual approaches, the probability of introducing logic bugs in the circuit is high, it would then be necessary to make use of verification and debugging techniques for the designed circuits. One of the classic verification methods is simulation. This approach is not suitable for large designs and it does... 

    Aging Mitigation for Arithmetic and Logic Unit of a Processor

    , M.Sc. Thesis Sharif University of Technology Sharifi, Ferdous (Author) ; Hesabi, Shahin (Supervisor)
    Abstract
    Shrinking the dimensions of transistors in recent fabrication technologies has led to an increase in the aging rate of chips, as the most important challenge in reliability of new processors. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effect of transistor shrinkage. These two effects decrease the switching speed of transistors by increasing its threshold voltage over time. Threshold voltage shift causes timing violation in combinational parts of circuit and decreases the robustness of sequential parts against soft errors. Between different units of a processor, Arithmetic and Logic Unit (ALU) is one of the most susceptible units... 

    Existence of Arithmetic Progressions in Subsets of Natural Numbers

    , M.Sc. Thesis Sharif University of Technology Zareh Bidaki, Mojtaba (Author) ; Rastegar, Arash (Supervisor) ; Hatami Varzaneh, Omid (Supervisor)
    Abstract
    Szemeredi's theorem is one of the significant theorems in additive combinatorics which was started by Van Der Waerden's theorem in 1927. Erdos and Turan conjectured generalized versions of Van Der Waerden's theorem in several ways included Szemeredi's theorem. In 1975 Szemeredi proved the conjecture using complicated combinatorial methods. In 1977 H. Furstenberg proved Szemeredi's theorem via the Ergodic theory approach which led to prove polynomial Szemeredi's theorem and multi-dimensional Szemeredi's theorem. The Ergodic approach is the only known approach so far to these generalizations of this theorem which is named Ergodic Ramsey theory and led to some other problems in Ergodic theory... 

    Distributed Verifiable Computing: Algorithms and Analysis

    , M.Sc. Thesis Sharif University of Technology Rahimi, Ali (Author) ; Maddah Ali, Mohammad Ali (Supervisor)
    Abstract
    Zero knowledge proofs allow a person (prover) to convince another person (verifier) that he has performed a specific computation on a secret data correctly, and has obtained a true answer, without having to disclose the secret data. QAP (Quadratic Arithmetic Program) based zkSNARKs (zero knowledge Succinct Non-interactive Argument of Knowledge) are a type of zero knowledge proof. They have several properties that make them attractive in practice, e.g. verifier's work is very easy. So they are used in many areas such as Blockchain and cloud computing. But yet prover's work in QAP based zkSNARKs is heavy, therefore, it may not be possible for a prover with limited processing resource to run... 

    Low-power arithmetic unit for DSP applications

    , Article International Symposium on System on Chip, SoC ; 31 October- 2 November , 2011 , pp. 68-71 ; ISBN: 9781457706721 Modarressi, M ; Nikounia, S. H ; Jahangir, A. H ; Sharif University of Technology
    Abstract
    DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

    The de jongh property for basic arithmetic

    , Article Archive for Mathematical Logic ; 2014 ; ISSN: 09335846 Ardeshir, M ; Mojtahedi, S. M ; Sharif University of Technology
    Abstract
    We prove that Basic Arithmetic, BA, has the de Jongh property, i.e., for any propositional formula A(p1,..., pn) built up of atoms p1,..., pn, BPC(Formula presented.)A(p1,..., pn) if and only if for all arithmetical sentences B1,..., Bn, BA(Formula presented.)A(B1,..., Bn). The technique used in our proof can easily be applied to some known extensions of BA  

    Desynchronization attack on RAPP ultralightweight authentication protocol

    , Article Information Processing Letters ; Volume 113, Issue 7 , 2013 , Pages 205-209 ; 00200190 (ISSN) Ahmadian, Z ; Salmasizadeh, M ; Aref, M. R ; Sharif University of Technology
    2013
    Abstract
    RAPP (RFID Authentication Protocol with Permutation) is a recently proposed and efficient ultralightweight authentication protocol. Although it maintains the structure of the other existing ultralightweight protocols, the operation used in it is totally different due to the use of new introduced data dependent permutations and avoidance of modular arithmetic operations and biased logical operations such as AND and OR. The designers of RAPP claimed that this protocol resists against desynchronization attacks since the last messages of the protocol is sent by the reader and not by the tag. This letter challenges this assumption and shows that RAPP is vulnerable against desynchronization... 

    A new approach for automatic test pattern generation in register transfer level circuits

    , Article IEEE Design and Test ; Volume 30, Issue 4 , 2013 , Pages 49-59 ; 21682356 (ISSN) Mirzaei, M ; Tabandeh, M ; Alizadeh, B ; Navabi, Z ; Sharif University of Technology
    2013
    Abstract
    The article proposes an approach to generate high-level test patterns from the arithmetic model of a register-transfer-level (RTL) circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. For simplification of a test procedure, some ATPG approaches have been introduced based on binary decision diagram (BDD) tools. Since these methods require the design to be flattened into the bit level, they cannot be used to deal with large industrial benchmarks efficiently, either in terms of memory or runtime.... 

    Low-power arithmetic unit for DSP applications

    , Article 2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015 ; 2011 , Pages 68-71 ; 9781457706721 (ISBN) Modarressi, M ; Nikounia, S. H ; Jahangir, A. H ; Sharif University of Technology
    Abstract
    DSP algorithms are one of the most important components of modern embedded computer systems. These applications generally include fixed point and floating-point arithmetic operations and trigonometric functions which have long latencies and high power consumption. Nonetheless, DSP applications enjoy from some interesting characteristics such as tolerating slight loss of accuracy and high degree of value locality which can be exploited to improve their power consumption and performance. In this paper, we present an application-specific result-cache that aims to reduce the power consumption and latency of DSP algorithms by reusing the results of the arithmetic operations executed on the same... 

    Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors

    , Article Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN) Fazeli, M ; Namazi, A ; Miremadi, S. G ; Haghdoost, A ; Sharif University of Technology
    2011
    Abstract
    This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

    Universal image steganalysis against spatial-domain steganography based on energy distribution of singular values

    , Article 7th International Conference on Information Technology and Application, ICITA 2011 ; 2011 , Pages 179-183 ; 9780980326741 (ISBN) Shojaei Hashemi, A ; Soltanian Zadeh, H ; Ghaemmagham, S ; Kamarei, M ; Sharif University of Technology
    Abstract
    A passive image steganalysis method is proposed to universally detect spatial-domain steganography schemes. It is shown to have better performance than universal steganalyzers known to be powerful in spatial domain, including the WFLogSv and the WAM methods. This level of accuracy is the result of improving the WFLogSv steganalyzer by considering a more comprehensive relationship between the singular values of each image block and the linear correlation of the rows and the columns. That is, instead of the closeness of the lower singular values to zero, the energy distribution of the singular values is investigated. An innovative measure is proposed for this investigation, which is inspired... 

    A novel voltage-to-voltage logarithmic converter with high accuracy

    , Article Przeglad Elektrotechniczny ; Volume 87, Issue 4 , 2011 , Pages 150-153 ; 00332097 (ISSN) Ghanaattian Jahromi, A ; Abrishamifar, A ; Medi, A ; Sharif University of Technology
    Abstract
    A novel BiCMOS voltage-to-voltage converter with logarithmic characteristics and very high accuracy is presented. The relationship between the emitter current and the base-emitter voltage in bipolar transistors is used to realize the logarithmic function. With 1.8 supply voltage, the total power consumption is less than 15.75 mW and a Log error of < -36dB is shown in the ADS simulations. Compared to the other method in the literature, very better accuracy in logarithm calculation is achieved. The proposed method can be used in arithmetical operation circuits like analog processors  

    Memristor-based circuits for performing basic arithmetic operations

    , Article Procedia Computer Science, 6 October 2010 through 10 October 2010 ; Volume 3 , October , 2011 , Pages 128-132 ; 18770509 (ISSN) Merrikh Bayat, F ; Shouraki, S. B ; Sharif University of Technology
    2011
    Abstract
    In almost all of the currently working circuits, especially in analog circuits implementing signal processing applications, basic arithmetic operations such as multiplication, addition, subtraction and division are performed on values which are represented by voltages or currents. However, in this paper, we propose a new and simple method for performing analog arithmetic operations which in this scheme, signals are represented and stored through a memristance of the newly found circuit element, i.e. memristor, instead of voltage or current. Some of these operators such as divider and multiplier are much simpler and faster than their equivalent voltage-based circuits and they require less... 

    What's decidable about availability languages?

    , Article 35th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2015, 16 December 2015 through 18 December 2015 ; Volume 45 , 2015 , Pages 192-205 ; 18688969 (ISSN) ; 9783939897972 (ISBN) Abdulla, P. A ; Atig, M. F ; Meyer, R ; Salehi, M. S ; Harsha P ; Ramalingam G ; Sharif University of Technology
    Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing  2015
    Abstract
    We study here the algorithmic analysis of systems modeled in terms of availability languages. Our first main result is a positive answer to the emptiness problem: it is decidable whether a given availability language contains a word. The key idea is an inductive construction that replaces availability languages with Parikh-equivalent regular languages. As a second contribution, we solve the intersection problem modulo bounded languages: given availability languages and a bounded language, it is decidable whether the intersection of the former contains a word from the bounded language. We show that the problem is NP-complete. The idea is to reduce to satisfiability of existential Presburger...