Sharif Digital Repository

A passive image steganalysis method is proposed to universally detect spatial-domain steganography schemes. It is shown to have better performance than universal steganalyzers known to be powerful in spatial domain, including the WFLogSv and the WAM methods. This level of accuracy is the result of improving the WFLogSv steganalyzer by considering a more comprehensive relationship between the singular values of each image block and the linear correlation of the rows and the columns. That is, instead of the closeness of the lower singular values to zero, the energy distribution of the singular values is investigated. An innovative measure is proposed for this investigation, which is inspired... 

In almost all of the currently working circuits, especially in analog circuits implementing signal processing applications, basic arithmetic operations such as multiplication, addition, subtraction and division are performed on values which are represented by voltages or currents. However, in this paper, we propose a new and simple method for performing analog arithmetic operations which in this scheme, signals are represented and stored through a memristance of the newly found circuit element, i.e. memristor, instead of voltage or current. Some of these operators such as divider and multiplier are much simpler and faster than their equivalent voltage-based circuits and they require less... 

In this paper, performance of grid computing environment is studied in the presence of failure-repair of the resources. To achieve this, in the first step, each of the grid resource is individually modeled using Stochastic Reward Nets (SRNs), and mean response time of the resource for grid tasks is computed as a performance measure. In individual models, three different scheduling schemes called random selection, non-preemptive priority, and preemptive priority are considered to simultaneously schedule local and grid tasks to the processors of a single resource. In the next step, single resource models are combined to shape an entire grid environment. Since the number of the resources in a... 

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a... 

In this paper we propose a novel OCR system which can recognize and calculate handwritten Persian arithmetic expressions without using a keyboard or a memory to store the intermediate results. Our research is composed of two major phases: character recognition and calculation. The recognition phase is based on a new approach for feature extraction. Fuzzy Support Vector Machines (FSVMs) are employed as the classifier. In calculation phase a simple algorithm is used for calculating the recognized arithmetic expression. The performance of the system is evaluated on a database consisting of 3400 digits and symbols written by 20 different people. 92 percent accuracy in recognition proves the good... 

In this paper, we propose a novel OCR system which can recognize and calculate handwritten Persian arithmetic expressions without using a keyboard or a memory to store the intermediate results. Our system is composed of two major phases: character recognition and calculation. The recognition phase is based on a new approach for feature extraction followed by a Fuzzy Support Vector Machines (FSVMs) as the classifier. In calculation phase a simple algorithm is used for calculating the recognized arithmetic expressions. The performance of the system was evaluated on a database consisting of 3400 digits and symbols written by 20 different people. 92 percent accuracy in recognition proves the... 

This paper presents a centralized fault detection algorithm for wireless sensor networks. Faulty sensor nodes are identified based on comparisons between neighboring nodes and own central node and dissemination of the decision made at each node. RNS system is used to tolerate transient faults in sensing and communication. In this system, arithmetic operations act on residues - reminder of dividing original number in several definite modules - in parallel. Consequently computations on these residues which are smaller than the original number are performed, so speed up arithmetic and decreased power consumption is achieved. ©2009 IEEE  

Inserting redundancy to arithmetic codes is a common strategy to add error detection capability to this well-known family of source codes. By using this strategy error correction is possible through some decoding algorithms such as Viterbi decoder. In this paper a system has proposed that uses finite state integer arithmetic codes (FSAC) as a joint source-channel code in combination with a cyclic redundancy check (CRC) and a List Viterbi decoder. The proposed scheme has shown better performance than previous ones. © 2009 IEEE  

As transistor dimensions continue to shrink, long-term reliability threats, such as Negative Bias Temperature Instability, affect multicore processors lifespan. This letter proposes a load balancing technique, based on the rate of integer and floating-point instructions per workloads. This technique classifies workloads into integer-majority and floating-point-majority classes and migrates workloads among cores in order to relax the stressed execution units. The context switching feature of operating system is employed to reduce implementation and performance overheads of the proposed technique. According to the simulations, the proposed technique reduces the aging rate of a multicore... 

This work provides a canonical representation for manipulation of RTL designs. Work has already been done on a canonical and graph-based representation called Taylor Expansion Diagram (TED). Although TED can effectively be used to represent arithmetic expressions at the word-level, it is not memory efficient in representing bit-level logic expressions. In addition, TED cannot represent Boolean expressions at the word-level (vector-level). In this paper, we present modifications to TED that will improve its ability for bit-level logic representation while enhancing its robustness to represent word-level Boolean expressions. It will be shown that for bit-level logic expressions, the Enhanced... 

While the Control Flow Checking (CFC) methods are using the ordinary instruction set and general Arithmetic and Logic Unit (ALU) features to protect the programs against the transient faults, this paper presents a new kind of CFC method, called feature specific CFC. The idea behind this method is using a specific internal hardware in modern processors which provides the ability to monitor internal various parameters of the program. This method is a pure software method and the external hardware overhead is zero. Other overheads have been measured experimentally by executing the workloads on a Pentium system. The execution time overhead is between 42% and 67% and the program size overhead is... 

Tolerance analysis is a key analytical tool for estimation of accumulating effects of the individual part tolerances on the design specifications of a mechanical assembly. This paper presents a new feature-based approach to tolerance analysis for mechanical assemblies with geometrical and dimensional tolerances. In this approach, geometrical and dimensional tolerances are expressed by small degrees of freedom (SDOF) of geometric entities (faces, feature axes, edges, and features of size) that are described by tolerance zones. The uncertainty of dimensions and geometrical form of features due to tolerances is mathematically described using modal interval arithmetic. The two concepts of modal... 

Infrastructure as a Service (IaaS) is one of the most significant and fastest growing fields in cloud computing. To efficiently use the resources of an IaaS cloud, several important factors such as performance, availability, and power consumption need to be considered and evaluated carefully. Evaluation of these metrics is essential for cost-benefit prediction and quantification of different strategies which can be applied to cloud management. In this paper, analytical models based on Stochastic Reward Nets (SRNs) are proposed to model and evaluate an IaaS cloud system at different levels. To achieve this, an SRN is initially presented to model a group of physical machines which are... 

This research work presents a low-level radio frequency (RF) control method based on the in-phase, I , and quadrature, Q , components of the RF signal. The proposed method uses only the main four arithmetic operations, i.e., addition, subtraction, multiplication, and division, which makes this control method suitable for implementation on the field-programmable gate array. The control scheme is adaptive in the sense that it estimates the system response on-the-fly, and therefore, it is robust against changes in the loop phase and/or gain during the operation. © 2017 IEEE  

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, xor extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted xors into half/full-adders to make a very fast debugging algorithm. This approach is... 

Infrastructure as a Service (IaaS) is one of the most significant and fastest growing fields in cloud computing. To efficiently use the resources of an IaaS cloud, several important factors such as performance, availability, and power consumption need to be considered and evaluated carefully. Evaluation of these metrics is essential for cost-benefit prediction and quantification of different strategies which can be applied to cloud management. In this paper, analytical models based on Stochastic Reward Nets (SRNs) are proposed to model and evaluate an IaaS cloud system at different levels. To achieve this, an SRN is initially presented to model a group of physical machines which are... 

Isogeny-based cryptography is one of the promising post-quantum candidates mainly because of its smaller public key length. Due to its high computational cost, efficient implementations are significantly important. In this paper, we have proposed a high-speed FPGA implementation of the supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE). To this end, we have adapted the algorithm of finding optimal large-degree isogeny computation strategy for hardware implementations. Using this algorithm, hardware-suited strategies (HSSs) can be devised. We have also developed a tool to schedule field arithmetic operations efficiently using constraint programming. This tool enables... 

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are...