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Total 167 records

    RISC-HD: lightweight risc-v processor for efficient hyperdimensional computing inference

    , Article IEEE Internet of Things Journal ; Volume 9, Issue 23 , 2022 , Pages 24030-24037 ; 23274662 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Hadayeghparast, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to... 

    A high performance real-time simulator for controllers hardware-in-the-loop testing

    , Article Energies ; Volume 5, Issue 6 , 2012 , Pages 1713-1733 ; 19961073 (ISSN) Matar, M ; Karimi, H ; Etemadi, A ; Iravani, R ; Sharif University of Technology
    2012
    Abstract
    This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The... 

    FPGA-based fault tolerant scheme with reduced extra-sensor number for WECS with DFIG

    , Article Proceedings - ISIE 2011: 2011 IEEE International Symposium on Industrial Electronics, 27 June 2011 through 30 June 2011 ; 2011 , Pages 1595-1601 ; 9781424493128 (ISBN) Shahbazi, M ; Gaillard, A ; Poure, P ; Zolghadri, M. R ; Sharif University of Technology
    2011
    Abstract
    Fast fault detection and converter reconfiguration is necessary for fault tolerant doubly fed induction generator (DFIG) in wind energy conversion systems (WECS) to prevent further damage and to make possible the continuity of service. Extra sensors are needed in order to detect the faults rapidly. In this paper, a very fast FPGA-based fault detection scheme is presented that minimizes the number of additional voltage sensors. A fault tolerant converter topology for this application is studied. Control and fault detection system are implemented on a single FPGA and Hardware in the Loop experiments are performed to evaluate the proposed detection scheme, the digital controller and the fault... 

    Implementation of MPC as an AQM controller

    , Article Computer Communications ; Volume 33, Issue 2 , 2010 , Pages 227-239 ; 01403664 (ISSN) Marami, B ; Haeri, M ; Sharif University of Technology
    Abstract
    Utilizing model predictive controllers (MPC) as an active queue management scheme is investigated in this paper. Model based prediction of future output and determining optimized value of the control signal have made MPC as an advanced control strategy in various modern control systems. In this paper a new approach is proposed to alleviate the computational complexity of MPC in order to implement in fast dynamics systems like computer networks. Neural network approximation of MPC as an active queue management (AQM) method implemented here not only has less computational burden with respect to the common MPC approaches, but also results in better performance compare to the well-known AQM... 

    An efficient hardware implementation for a motor imagery brain computer interface system

    , Article Scientia Iranica ; Volume 26, Issue 1 , 2019 , Pages 72-94 ; 10263098 (ISSN) Malekmohammadi, A ; Mohammadzade, H ; Chamanzar, A ; Shabany, M ; Ghojogh, B ; Sharif University of Technology
    Sharif University of Technology  2019
    Abstract
    Brain Computer Interface (BCI) systems, which are based on motor imagery, enable humans to command artificial peripherals by merely thinking about the task. There is a tremendous interest in implementing BCIs on portable platforms, such as Field Programmable Gate Arrays (FPGAS) due to their low-cost, low-power and portability characteristics. This article presents the design and implementation of a Brain Computer Interface (BCI) system based on motor imagery on a Virtex-6 FPGA. In order to design an accurate algorithm, the proposed method avails statistical learning methods such as Mutual Information (MI), Linear Discriminant Analysis (LDA), and Support Vector Machine (SVM). It also uses... 

    High-Speed post-quantum cryptoprocessor based on RISC-V architecture for IoT

    , Article IEEE Internet of Things Journal ; Volume 9, Issue 17 , 2022 , Pages 15839-15846 ; 23274662 (ISSN) Hadayeghparast, S ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Public-key plays a significant role in today's communication over the network. However, current state-of-the-art public-key encryption (PKE) schemes are too complex to be efficiently employed in resource-constrained devices. Moreover, they are vulnerable to quantum attacks and soon will not have the required security. In the last decade, lattice-based cryptography has been a progenitor platform of the post-quantum cryptography (PQC) due to its lower complexity, which makes it more suitable for Internet of Things applications. In this article, we propose an efficient implementation of the binary learning with errors over ring (Ring-BinLWE) on the reduced instruction set computer-five (RISC-V)... 

    Cellular underwater wireless optical CDMA network: Performance analysis and implementation concepts

    , Article IEEE Transactions on Communications ; Volume 63, Issue 3 , 2015 , Pages 882-891 ; 00906778 (ISSN) Akhoundi, F ; Salehi, J. A ; Tashakori, A ; Sharif University of Technology
    Abstract
    In this paper, we introduce and investigate a cellular underwater wireless optical code division multiple-access (OCDMA) network based on optical orthogonal codes (OOC). The structures, principles, and performance of the underwater wireless OCDMA network in various water types are presented. Since underwater wireless optical links are considered for high-bandwidth underwater communications at short ranges, we will place a set of optical base transceiver stations (OBTS) each in the center of a hexagonal cell to cover a larger underwater area. The OBTSs are connected via fiber optic to an optical network controller (ONC) which operates as the core of the network. An integral expression for...