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    Runtime Analysis of Self-adaptive Systems

    , Ph.D. Dissertation Sharif University of Technology Bagheri, Maryam (Author) ; Movaghar, Ali (Supervisor) ; Sirjani, Marjan (Supervisor)
    Abstract
    Increasing the complexity of software systems, their ubiquitous presence in the human activities, and necessity to preserving the functional and nonfunctional requirements of the systems under an uncertain environment, increase the need for self-adaptive systems. A self-adaptive system changes its structure and behaviors in response to changes in its environment and the system itself. A key research challenge in the self-adaptive community is to guarantee that the system fulfills its requirements. This issue can be addressed by employing formal methods during the design of the software systems. However, the assurance techniques should be used during the execution of the system as well as the... 

    Using intra-line level pairing for graceful degradation support in PCMs

    , Article Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 8 July 2015 through 10 July 2015 ; Volume 07-10-July-2015 , 2015 , Pages 527-532 ; 21593469 (ISSN) ; 9781479987184 (ISBN) Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    IEEE Computer Society  2015
    Abstract
    In Phase-Change Memory (PCM), the number of writes a cell can take before wearing-out is limited and highly varied due to unbalanced write traffic and process variation. After the failure of weak cells and in presence of large number of failed lines, some techniques have been proposed to further prolong the lifetime of a PCM device by remapping failed lines to spares and salvage a PCM device with graceful degradation. Others rely on handling failures through inter-line pairing. Observations reveal that most of cells in a line are healthy when the line is marked as faulty by any of these proposals. To overcome this deficiency, we propose Intra-line Level Pairing(ILP), a technique that... 

    Addressing issues with MLC phase-change memory

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 111-133 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    All of the presented solutions in this book focused on using MLC phase change memory (PCM) due to density advantage and prolonging PCM lifetime. However, resistance drift can be one of the challenging issues for MLC PCMs. While it is desired to have the density advantage of MLC, the trade-off is resistance drift. Since MLCs have closely separated resistance regions, drift has a chance of overlapping intermediate regions. It may then bring out either single bit or multi-bit soft error. Indeed, drift source is related to the semi amorphous resistance regions that are metastable vs time and temperature while crystalline resistance proves to be stable across time and temperature. This chapter... 

    Handling hard errors in PCMs by using intra-line level schemes

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 79-109 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    In this chapter, we first introduce one shifting mechanisms in order to further prolonging the lifetime of a phase change memory (PCM) device, reducing the write rate to PCM cells, and handling cell failures when hard faults occur. In this line, Byte-level Shifting Scheme (BLESS) is addressed and reduces write pressure over hot cells of blocks. Additionally, we illustrate that using the MLC capability of PCM and manipulating the data block to recover faulty cells can also be used for error recovery purpose. Next, we propose another intra-line level pairing scheme (ILP). This novel recovery mechanism can statically partition a data block into a small number of groups and efficiently benefits... 

    Introduction to non-volatile memory technologies

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 1-13 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    Dynamic Random Access Memory (DRAM) has been the leading main memory technology during the last four decades. In deep submicron regime, however, scaling DRAM comes with several challenges caused by charge leakage and imprecise charge placement. Phase Change Memory (PCM) technology is known as one of the most promising technologies to replace DRAM. Compared to competitive non-volatile memories like NAND Flash, Spin Transfer Torque random-access memory (STT-RAM), Magnetoresistive random-access memory (MRAM), PCM benefits from best attributes of fast random access, negligible leakage energy, superior scalability, high density, and operating in both Single-level Cell (SLC) and Multilevel Cell... 

    Inter-line level schemes for handling hard errors in PCMs

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 49-78 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    To address the problem of fast degradation in PCM main memory systems in the presence of severe cell wear-out, this chapter introduces and evaluates some ways to deal with hard error issues in phase change memory. Our observation reveals when some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. In this chapter, we also propose On-demand page paired PCM (OD3P) memory system. Our technique mitigates the problem of fast failure of pages by redirecting them onto other healthy pages,... 

    Phase-change memory architectures

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 29-48 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    Some of the recent approaches regarding leverage PCM will be reviewed in this chapter. The chapter starts with a discussion regarding future main memory systems that includes hybrid architecture schemes using both PCM and DRAM arrays. Later, we focus on PCM only approaches and this section will help describe some techniques for reducing the increased read latency because of slow writes in PCMs. In this chapter, we also illustrate wear-leveling approaches and review the security problems of this memory approach which are lifetime limited. This section includes an overview of the recent security aware wear-leveling techniques, whose methods help detect attacks, and their issues during the... 

    The emerging phase change memory

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 15-28 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    This chapter evaluates viewpoints on the Phase Change Memory (PCM) devices and materials entailing multi-level cell (MLC) phase change memory as well as its trade-offs. This chapter lists the main difficulties related to PCMs and possible recommendations to address those challenges. The next chapters introduce some simple techniques to alleviate some of the problems listed here. © 2020 Elsevier Inc  

    Design and Manufacturing of Gradient Cellular Tibial Stem for Total Knee Replacement

    , M.Sc. Thesis Sharif University of Technology Taheri, Atiyeh (Author) ; Farahmand, Farzam (Supervisor) ; Bahrami Nasab, Marjan (Co-Supervisor)
    Abstract
    Loosening of uncemented tibial component is one the most common causes of total knee prosthesis failure which is a result of short-term factors such as instability and incomplete osseointegration as well as long-term factors such as peri-prosthetic stress shielding and bone atrophy. Porous cellular structures for tibial stem have been considered as a solution to this problem. This project is aimed to achieve an optimal gradient porous cellular design of tibial stem that in addition to sufficient mechanical strength, provides a perfect osseointegration and prevents bone resorption by incorporating appropriate porosity size, small micro-motion and favorable stress distribution on bone. A... 

    Theoretical Investigation of Quantum Optical Amplifiers in Quantum Communications

    , M.Sc. Thesis Sharif University of Technology Marjan, Negar (Author) ; Bahrampour, Alireza (Supervisor) ; Bathaee, Marzieh Sadat (Co-Supervisor)
    Abstract
    Signal transmission of information on noiseless and lossy channels is an important issue in data transmission. Using the amplifier in the transmission channels is a good solution to help send information on longer channels. In classical communication, information can be coded in the amplitude or phase of the field and an amplifier is responsible for amplifying these parameters. If we consider the conditions ideal and ignore electrical noises, Classical mechanics does not impose any restrictions on the amplification of arbitrary classical signals. Instead, in quantum telecommunications the information encoded on the quadrature of the electromagnetic field are mounted on quantum states, such... 

    Prolonging lifetime of PCM-based main memories through on-demand page pairing

    , Article ACM Transactions on Design Automation of Electronic Systems ; Vol. 20, issue. 2 , 1 February , 2015 ; ISSN: 10844309 Asadinia, M ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    2015
    Abstract
    With current memory scalability challenges, Phase-Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that results in fast wear-out of memory cells. Worse, process variation in the deep-nanometer regime increases the variation in cell lifetime, resulting in an early and sudden reduction in main memory capacity due to the wear-out of a few cells. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer poor throughput or latency. In this article, we show that one of the inefficiency sources in current schemes, even when wear-leveling algorithms are used,... 

    OD3P: On-demand page paired PCM

    , Article Proceedings - Design Automation Conference ; 2-5 June , 2014 , pp. 1-6 ; ISSN: 0738100X ; ISBN: 9781450327305 Asadinia, M ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    2014
    Abstract
    With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by pro-cess variation in nanometer regime. This increases the vari- ation in cell lifetime resulting in early and sudden reduc- tion in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redi- rection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we... 

    Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links

    , Article IET Computers and Digital Techniques ; Vol. 6, issue. 5 , September , 2012 , pp. 302-317 ; ISSN: 17518601 Asadinia, M ; Modarressi, M ; Sarbazi-Azad, H ; Sharif University of Technology
    2012
    Abstract
    In this study, the authors propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a chip multiprocessor, when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the network-on-chip employed as the communication infrastructure. In this work, the authors benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application mapped onto disjoint regions (submeshes) and then virtually connecting them by bypassing the... 

    OD3P: On-demand page paired PCM

    , Article Proceedings - Design Automation Conference ; 2014 Asadinia, M ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    2014
    Abstract
    With current memory scalability challenges, Phase Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that is highly affected by pro-cess variation in nanometer regime. This increases the vari- ation in cell lifetime resulting in early and sudden reduc- tion in main memory capacity due to wear-out of few cells. When some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redi- rection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. On contrary, we... 

    Prolonging lifetime of PCM-based main memories through on-demand page pairing

    , Article ACM Transactions on Design Automation of Electronic Systems ; Volume 20, Issue 2 , 2015 ; 10844309 (ISSN) Asadinia, M ; Arjomand, M ; Azad, H. S ; Sharif University of Technology
    Association for Computing Machinery  2015
    Abstract
    With current memory scalability challenges, Phase-Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that results in fast wear-out of memory cells. Worse, process variation in the deep-nanometer regime increases the variation in cell lifetime, resulting in an early and sudden reduction in main memory capacity due to the wear-out of a few cells. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer poor throughput or latency. In this article, we show that one of the inefficiency sources in current schemes, even when wear-leveling algorithms are used,... 

    BLESS: A simple and efficient scheme for prolonging PCM lifetime

    , Article 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN) Asadinia, M ; Jalili, M ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    Limited endurance problem and low cell reliability are main challenges of phase change memory (PCM) as an alternative to DRAM. To further prolong the lifetime of a PCM device, there exist a number of techniques that can be grouped in two categories: 1) reducing the write rate to PCM cells, and 2) handling cell failures when faults occur. Our experiments confirm that during write operations, an extensive non-uniformity in bit ips is exhibited. To reduce this non-uniformity, we present byte-level shifting scheme (BLESS) which reduces write pressure over hot cells of blocks. Additionally, this shifting mechanism can be used for error recovery purpose by using the MLC capability of PCM and... 

    Data block partitioning for recovering stuck-at faults in PCMs

    , Article 2017 IEEE International Conference on Networking, Architecture, and Storage, NAS 2017 - Proceedings, 7 August 2017 through 9 August 2017 ; 2017 ; 9781538634868 (ISBN) Asadinia, M ; Jalili, M ; Sarbazi Azad, H ; Sharif University of Technology
    2017
    Abstract
    Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter-line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in... 

    Supporting Non-Contiguouse Processor Allocation in Mesh-based CMPs

    , M.Sc. Thesis Sharif University of Technology Asadinia, Marjan (Author) ; Sarbazi-Azad, Hamid (Supervisor)
    Abstract
    In this thesis, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution life-time of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the Network-on-Chip (NoC). In this work, we benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application to be mapped onto disjoint regions (sub-meshes) and then virtually connecting them by bypassing the router pipeline stages of inter-region... 

    Improving Reliability and Durability of Phase Change Main Memories

    , M.Sc. Thesis Sharif University of Technology Asadinia, Marjan (Author) ; Sarbazi Azad, Hamid (Supervisor)
    Abstract
    Dynamic Random Access Memory (DRAM) has been the leading main memory technology during the last four decades. In deep sub-micron regime, however, scaling DRAM comes with several challenges caused by charge leakage and imprecise charge placement. Phase Change Memory (PCM) technology is known as one of the most promising technologies to replace DRAM. Compared to competitive non-volatile memories, PCM benefits from best attributes of fast random access, negligible leakage energy, superior scalability, high density, and operating in both Single-level Cell (SLC) and Multi-level Cell (MLC) storage levels without imposing large storage overhead. Unfortunately, density advantage of MLC PCM devices... 

    Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links

    , Article Proceedings -Design, Automation and Test in Europe, DATE ; 2011 , p. 413-418 ; ISSN: 15301591 ; ISBN: 9783981080179 Asadinia, M ; Modarressi, M ; Tavakkol, A ; Sarbazi-Azad, H ; Sharif University of Technology
    2011
    Abstract
    In this paper, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution lifetime of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the NoC employed as the communication infrastructure. In this work, we benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application mapped onto disjoint regions (sub-meshes) and then virtually connecting them by bypassing the router pipeline stages of...