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Proposing a Combined BTB and Data Cache Architecture for Modern Processors

Baradaran, Morteza | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43761 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Modern pipelined processors use a memory array named Branch Target Buffer (BTB) to reduce the performance penalty due to conditional braches by predicting path of the branch and keeping useful history-based information for future accesses. Today BTB is a fixed size and small memory array located near the processor. By the way, BTB, in the best case, should be large enough to accommodate all conditional branches throughout the running program. Moreover, small size BTB presents much fast access and is practical on-chip storage for a system with limited power budget.
    Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache hit ratio and access latency. In the current micro-processor architectures, the cache structure is usually organized as a set-associative memory array which suffers from non-uniform distribution of the memory references hashed into different sets during different program execution epochs: while some sets are rarely referenced and show high hit ratio, some others are highly referenced and may meet consecutive misses.
    To simultaneously address the shortcomings of the BTB and set-associative data cache, the current study presents a middle-ware architecture named as Common Victim Memory, CVM for short, which holds the evicted BTB and data cache blocks in the same structure for future references. The advantage of the proposed common memory organization is its capability of dynamically balancing access pattern to both cache and BTB structures. For evaluation and exploring design space of the proposed architecture, we have used MULTI2SIM simulator over diverse multi-threaded and multi-programmed benchmarks which shows up to 95 percent improvement in BTB hit ratio and nearly no degradation in cache access time compared to baseline systems
  9. Keywords:
  10. Efficiency ; Data Cache ; Branch Target Buffer (BTB) ; Associativity

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