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- Type of Document: Ph.D. Dissertation
- Language: Farsi
- Document No: 50779 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Miremadi, Ghasem; Ejlali, Alireza
- Abstract:
- Despite the advantages of shrinking transistors’ dimensions, e.g. decrease in power consumption and fabrication cost and increase in their switching speed, it has an adverse impact on some characteristics of nano-scale (less than 130nm) transistors that can reduce the system lifetime. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effects of transistor shrinkage. These two effects, are known as transistor aging, decrease the switching speed of the transistors by increasing the threshold voltage and decreasing the charge carriers’ mobility in the channel of transistors. Temperature, operating voltage, and the size of transistors have considerable impacts on BTI and HCI. Due to these aging effects, nowadays a guardband of 20% for operational frequency and voltage is required to ensure the safe operation of digital chips. Otherwise, timing violation that can lead to hard errors might occur. Besides the negative impact on timing, aging has an adverse influence on the reliability of sequential parts and decreases their robustness against soft errors. By controlling the effective factors on the aging phenomenon, some aging mitigation techniques have been proposed in the literature. However, guardbanding is still the most common technique to mitigate aging because of its relative effectiveness and low overhead. In this thesis, several techniques have been proposed to mitigate aging in critical parts of processors. To this end, the stress condition of each part of the processor has been analyzed regarding the most important aging phenomenon in that part. Five stages have been considered in this research project: i) Developing a compact and self-consistent model for aging prediction, ii) Devising aging sensors to monitor the aging condition of different parts of the chip, ii) Providing techniques to mitigate aging of sequential parts in processors, iv) Providing techniques to ameliorate the aging of interconnections, and v) Providing techniques to mitigate the aging of combinational parts in processor. The experimental setup and toolchain to analyze the proposed techniques includes gem5, CACTI, HotSpot, HSPICE, HiSIM, and ModelSim simulators plus Design Compiler and Virtuoso tool sets. The proposed aging sensor for combinational parts, with the area overhead of less than 33% in comparison with the smallest aging sensor in the previous work, delivers the accuracy of more than 2.7x in comparison with the most accurate aging sensor, presented in the previous work. Furthermore, the proposed aging mitigation techniques boost the lifetime of cache memories, Networks on Chip, and the combinational units of processor by 48%, 56%, and 3.5x, respectively
- Keywords:
- Aging ; Cache Memory ; Bias Temperature Instability (BTI) ; Process ; Reliability Improvment ; Processors ; Hot Carrier Injection (HCI)
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