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A 4-Bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation

Chahardori, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2013.2246206
  3. Publisher: 2013
  4. Abstract:
  5. A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after calibration. The converter offers 3.8 effective number of bits (ENOB) at 1.6 GS/s sampling rate with a low frequency input signal and more than 1.8 GHz effective resolution bandwidth (ERBW) at this sampling rate. The converter consumes mere 15.5 mW from a 1.8 V supply, yielding an FoM of 695 fJ/conversion.step and occupies 0.3 mm2 in a 0.18 μm standard CMOS process
  6. Keywords:
  7. Effective number of bits ; Power reduction techniques ; Effective resolution bandwidths ; FLASH-ADC ; Low Power ; Offset calibration ; Conventional structures ; Reference voltage generator ; Calibration ; CMOS integrated circuits ; Orthogonal frequency division multiplexing ; Analog to digital conversion
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 9 , 2013 , Pages 2285-2297 ; 15498328 (ISSN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6487420