Loading...

A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria

Saeidi, R ; Sharif University of Technology

801 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2011.5937501
  3. Abstract:
  4. This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify the proposed technique, a 64128 bit array of the 6T bit-cell is simulated in 90 nm CMOS technology. The simulation results show a 100% noise margin enhancement at subthreshold region. This design operates down to 300 mV at a 1 MHz clock rate with noise margins as large as 72 mV. This design demonstrates significant improvement in the read stability against the conventional 6T SRAM approach without requiring extra cell transistors
  5. Keywords:
  6. 6T-SRAM ; Activation time ; Bit lines ; Cell mismatch ; Cell transistor ; Clock rate ; CMOS technology ; Fundamental limits ; High-density ; Leakage problems ; Noise margins ; Poor stability ; Read operation ; Read stability ; Recovery time ; Simulation result ; Subthreshold ; Subthreshold dynamics ; Subthreshold region ; Wordlines ; CMOS integrated circuits ; Stability criteria
  7. Source: Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 61-64 ; 02714310 (ISSN) ; 9781424494736 (ISBN)
  8. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5937501