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A Micro-FT-UART for safety-critical SoC-based applications

Razmkhah, M. H ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/ARES.2009.43
  3. Publisher: 2009
  4. Abstract:
  5. This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09- SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering tradeoff between reliability and power consumption, an optimum faulttolerant technique is assigned to each part to design the micro-FT-UART. This UART corrects all single-bit errors and on average 24% of multiple-bit errors with about 81% power consumption overhead and 152% area overhead. © 2009 IEEE
  6. Keywords:
  7. Fault tolerance ; Low power ; SoC ; UART ; Area overhead ; Bit-errors ; Design compiler ; Error sensitivity ; Experimental study ; Fault-tolerant ; Hamming code ; Modelsim ; Power Consumption ; Safety-critical ; Single-bit ; Soft error ; Synopsys ; Triple modular redundancy ; VHDL-model ; Bit error rate ; Electric power utilization ; Error correction ; Fault tolerant computer systems ; Programmable logic controllers ; Quality assurance
  8. Source: International Conference on Availability, Reliability and Security, ARES 2009, Fukuoka, Fukuoka Prefecture, 16 March 2009 through 19 March 2009 ; 2009 , Pages 316-321 ; 9780769535647 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/5066488