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A low-power high-speed comparator for precise applications

Khorami, A ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TVLSI.2018.2833037
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process-VDDerature corners, and Monte Carlo simulations along with silicon measurements in 0.18 μm. The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input Vcm range in fclk = 500 MHz. © 2018 IEEE
  6. Keywords:
  7. Dynamic comparator ; Low-offset comparator ; Two-stage comparator ; Budget control ; Clocks ; Comparators (optical) ; Electric power utilization ; Intelligent systems ; Monte Carlo methods ; Dynamic comparators ; High Speed ; Low offset ; Low Power ; Two-stage ; Comparator circuits
  8. Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 26, Issue 10 , 2018 , Pages 2038-2049 ; 10638210 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8360153