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Low-latency double point multiplication architecture using differential addition chain over GF( 2 m)

Shahroodi, T ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2018.2883557
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5, and Virtex-7 over GF(2 163 ), GF(2 233 ), and GF(2 283 ), respectively. Experimental results using hardware implementation on Virtex-4 indicate that the proposed architecture achieves 63% and 16% improvements compared with the previous double point multiplication implementation in terms of required time and efficiency over GF(2 233 ), respectively. Additionally, the proposed architecture shows time reduction compared with twice the execution time of the best previous single point multiplication by 39% while achieving 258% higher efficiency. The proposed architecture has also been implemented on ASIC, and the results show that the proposed work improves time and energy consumption compared with the previous work
  6. Keywords:
  7. Binary fields ; Differential addition chain ; Double point multiplication ; Elliptic curve cryptography ; Computer hardware ; Energy utilization ; Field programmable gate arrays (FPGA) ; Geometry ; Hand held computers ; Hardware ; Public key cryptography ; Addition chains ; Complexity theory ; Point multiplication ; Computer architecture
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 4 , 2019 , Pages 1465-1473 ; 15498328 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8584471