Loading...

A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity

Saeedi, S ; Sharif University of Technology | 2005

196 Viewed
  1. Type of Document: Article
  2. DOI: 10.1007/s10470-005-6787-0
  3. Publisher: 2005
  4. Abstract:
  5. A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies a track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to 14-bit specification are less than 0.35 and 0.25 LSB respectively. The DAC is functional up to 400MS/s with SFDR better than 71 dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18 u CMOS technology. © Springer Science + Business Media Inc. 2005
  6. Keywords:
  7. Attenuation ; Bit error rate ; Calibration ; CMOS integrated circuits ; Computer simulation ; Electric potential ; Linearization ; Technology transfer ; Analog self calibration ; Current steering ; Enhanced dynamic linearity ; Error measurement ; Digital to analog conversion
  8. Source: Analog Integrated Circuits and Signal Processing ; Volume 43, Issue 2 , 2005 , Pages 137-145 ; 09251030 (ISSN)
  9. URL: https://link.springer.com/article/10.1007/s10470-005-6787-0