Sharif Digital Repository

Let Δ be a simplicial complex and χ be an s-coloring of Δ. Biermann and Van Tuyl have introduced the simplicial complex Δχ. As a corollary of Theorems 5 and 7 in their 2013 article, we obtain that the Stanley–Reisner ring of Δχ over a field is Cohen–Macaulay. In this note, we generalize this corollary by proving that the Stanley–Reisner ideal of Δχ over a field is set-theoretic complete intersection. This also generalizes a result of Macchia  

We study here the algorithmic analysis of systems modeled in terms of availability languages. Our first main result is a positive answer to the emptiness problem: it is decidable whether a given availability language contains a word. The key idea is an inductive construction that replaces availability languages with Parikh-equivalent regular languages. As a second contribution, we solve the intersection problem modulo bounded languages: given availability languages and a bounded language, it is decidable whether the intersection of the former contains a word from the bounded language. We show that the problem is NP-complete. The idea is to reduce to satisfiability of existential Presburger... 

Abstract BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication scheme to accelerate this module. Similar to previous articles, our multiplier includes two parts contained binary multiplier and binary to BCD converter. Our contribution towards these modules can successfully overcome the previous BCD digit multipliers. The results indicate 19% hardware acceleration for the proposed multiplier architecture which is comparable to the best previous techniques in UMC 65 nm CMOS standard cells library hardware implementation. Therefore, the proposed BCD digit multiplier is an... 

This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different... 

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm... 

RAPP (RFID Authentication Protocol with Permutation) is a recently proposed and efficient ultralightweight authentication protocol. Although it maintains the structure of the other existing ultralightweight protocols, the operation used in it is totally different due to the use of new introduced data dependent permutations and avoidance of modular arithmetic operations and biased logical operations such as AND and OR. The designers of RAPP claimed that this protocol resists against desynchronization attacks since the last messages of the protocol is sent by the reader and not by the tag. This letter challenges this assumption and shows that RAPP is vulnerable against desynchronization... 

The article proposes an approach to generate high-level test patterns from the arithmetic model of a register-transfer-level (RTL) circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. For simplification of a test procedure, some ATPG approaches have been introduced based on binary decision diagram (BDD) tools. Since these methods require the design to be flattened into the bit level, they cannot be used to deal with large industrial benchmarks efficiently, either in terms of memory or runtime.... 

Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over GF(2m). Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications  

In this paper, we propose two lossless compression techniques that represent a two dimensional Run-length Coding which can achieve high compression ratio. This method works by partitioning the block regions of the input image into rectangles instead of working by runs of adjacent pixels, so it is found to be more efficient than 1D RLE Run-length Coding for transmitting texts and image. In the first method, length and width of consecutive black and white rectangles are transmitted. The idea of this method is new and it can be very effective for some images which have large blocks of black or white pixels. But in the second method only black rectangles are considered in order to transmit and... 

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signalmapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust... 

The Boolean satisfiability problem plays a central role in computational complexity and is often used as a starting point for showing NP lower bounds. Generalisations such as Succinct SAT, where a Boolean formula is succinctly represented as a Boolean circuit, have been studied in the literature in order to lift the Boolean satisfiability problem to higher complexity classes such as NEXP. While, in theory, iterating this approach yields complete problems for k-NEXP for all k > 0, using such iterations of Succinct SAT is at best tedious when it comes to proving lower bounds. The main contribution of this paper is to show that the Boolean satisfiability problem has another canonical... 

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the...