Sharif Digital Repository

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration... 

Advanced Encryption Standard (AES) is the most popular symmetric encryption method, which encrypts streams of data by using symmetric keys. The current preferable AES architectures employ effective methods to achieve two important goals: protection against power analysis attacks and high-throughput. Based on a different architectural point of view, we implement a particular parallel architecture for the latter goal, which is capable of implementing a more efficient pipelining in field-programmable gate array (FPGA). In this regard, all intermediate registers which have a role for unrolling the main loop will be removed. Also, instead of unrolling the main loop of AES algorithm, we implement... 

A novel architecture for QR decomposition-based recursive least squares is presented. It offers low latency for applications where the channel equalization and adaptive filtering are mandatory. This approach reduces the computations by rewriting the equations in a manner that lets intense hardware resource sharing by reusing similar values in different computations. Moreover, precision range conversion allows for combining complex operations such as root square and division with minimum effect on the overall quantization error. Hence, an efficient lookup table-based solution has highly enhanced the performance of the design by 2.7 times with respect to the previous works  

Application of piezoelectric materials in vibration energy harvesters is expanding rapidly, especially in MEMS-based devices, due to their uncomplicated fabrication processes and reasonable power generation potential. In addition to standard power extraction methods, nonlinear switched techniques with capability of generated power enhancement, are previously developed and extensively applied in energy harvesting using piezoelectric materials. In this article, vibratory behavior of bimorph resonant harvesters coupled to nonlinear circuits of energy harvesting including standard and switched techniques is investigated. An analytical approach employing some perturbation technique, is utilized... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

Stimuli-responsive controlled-release nanocarriers are promising vehicles for delivery of bioactive molecules that can minimize side effects and maximize efficiency. The release of the drug occurs when the nanocarrier is triggered by an internal or external stimulus. Mesoporous silica nanoparticles (MSN) can have drugs and bioactive cargos loaded into the high-capacity pores, and their release can be triggered by activation of a variety of stimulus-responsive molecular "gatekeepers" or "nanovalves." In this mini-review, we discuss the basic concepts of MSN in targeted drug-release systems and cover different stimulus-responsive gatekeepers. Internal stimuli include redox, enzymes, and pH,... 

This paper used a 4-level frequency shift keying (4-FSK) modulation scheme to enhance the density of wireless data transfer from implantable biomedical microsystems to the outside world. Modeling and simulation of the wireless channel for 4-FSK modulation in the case of a neural recording implant has been done. To realize the 4-FSK scheme, the modulator and demodulator circuits are proposed, designed and simulated in a 0.18-μm CMOS process, and in the 174-216 MHz frequency band at a data rate of 13.5 Mbps. Operated using a 1.8 V supply voltage, the modulator circuit consumes a power of 7.8 μW  

The study of water hammer in air-water, two-phase flows in hydraulic structures such as pressurized pipelines and tunnels, siphons, culverts, and junctions is of great importance for design purposes. Water hammer if combined with a periodic slug flow would lead to severe periodic transient pressure fluctuations inside the conduit. Laboratory experiments have been conducted to investigate waterhammer pressure inside a horizontal rectangular conduit carrying a two-phase, air-water slug flow. Tests were performed in an experimental apparatus comprising a 6.8-m-long transparent pipeline 0.06 m wide and 0.1 m high. By rapidly closing a control gate at the end of the conduit, propagating pressure... 

Considering the two main categories of rapid single flux quantum gates with destructive and nondestructive readout process, we have investigated the effects of readout cell topology and involved critical parameters on the proper functionality and stability of the states of the newly developed bidirectional T flip-flops (TFFs). It is observed that instabilities and fluctuations in the state of the gate (memory of TFF) after each transition determine the minimum time intervals between the clock pulses set by the ac bias current, further limiting the ultimate operation frequency of the circuits. The absolute values of the current levels of the junctions at each state, which play an important... 

Application of piezoelectric materials in vibration energy harvesters is expanding rapidly, especially in MEMS-based devices, due to their uncomplicated fabrication processes and reasonable power generation potential. In addition to standard power extraction methods, nonlinear switched techniques with capability of generated power enhancement, are previously developed and extensively applied in energy harvesting using piezoelectric materials. In this article, vibratory behavior of bimorph resonant harvesters coupled to nonlinear circuits of energy harvesting including standard and switched techniques is investigated. An analytical approach employing some perturbation technique, is utilized... 

In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital... 

Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable... 

FPGA-based multiprocessors, referred as softmultiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in the configuration bits. The main of this method is to analyze the scheduled task graph and select a subset of tasks to be replicated in multiple processors based on the utilization of the processors in different execution phases. To this end, 1) errors are detected by re-executing a subset of tasks... 

This paper initially deals with the design of a new customized reconfigurable mobile parallel mechanism. This mechanism is called "Taar Reconfigurable ParaMobile (TRPM)", consisting of three mobile robots as the main actuators. Then, the kinematics and path planning for this mechanism are represented. The newly proposed mechanism is expected to circumvent some shortcomings of inspection operation in unknown environments with unexpected changes in their workspace, e.g., in a water pipe with non-uniform section area. In this paper, "Artificial Potential Field (APF)" has been assumed to be the path planning algorithm and its resulting attractive and repulsive forces are only applied to the... 

In this paper, a decentralized controller for trajectory tracking of modular and reconfigurable robot manipulators is developed. The proposed control scheme uses joint-torque sensory feedback; also sliding mode control is employed to make both position and velocity tracking errors of robot manipulators globally converging to zero. Proposed scheme also guarantees that all signals in closed-loop systems will be bounded. In contrast to some of prior works in this scheme, each controller uses a smooth law to achieve its purposes. In this method, each controller uses only local information for producing control law hence separated controller can be used to control each module of manipulator and... 

There has been an increasing interest in telemonitoring thanks to the availability of new technologies for data transmission and processing with better performances and lower costs. In this paper, we try to develop and implement the HRV signal processing into a Field Programmable Gate Array (FPGA). The hardware implementing algorithm was developed in Verilog Hardware Description Language (HDL). In designed hardware, after defining the number of samples in the input, we extract and analyses the Triangular Phase Space Mapping (TPSM), a novel method for representation of heart rate. The performance of the system was tested using MATLAB and validated based on the input signals  

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling... 

Data traversal in Network-on-Chips (NoCs) is threated by crosstalk fault seriously. Crosstalk fault leads to mutual influence between adjacent wires of NoCs and as a result endangers the reliability of data in NoCs. Crosstalk fault is strongly dependent on the transition patterns appearing on the wires of NoCs. Among these transitions, Triplet Opposite Directions (TODs) impose the worse crosstalk effects to the wires of NoCs. This paper proposes an efficient numerical-based coding mechanism called Summation-based-Subtracted-Added-Penultimate (S2AP) which alleviates crosstalk faults. This is done by completely removing TODs which are the main source of crosstalk faults in the channels of...