Loading...

A low power 1-V 10-bit 40-MS/s pipeline ADC

Hashemi, M ; Sharif University of Technology | 2011

1281 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2011.6122251
  3. Publisher: 2011
  4. Abstract:
  5. A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC achieves 56.04dB signal-to-noise ratio (SNDR), 9.02 effective numbers of bits (ENOB) and INL/DNL of less than 1 LSB, while consuming only 3.9 mW from a 1-V power supply. The Figure-of-Merit (FOM) value is less than 0.19 pJ/Conversion
  6. Keywords:
  7. Back-end design ; Circuit levels ; Class A ; CMOS technology ; Customized software ; Effective Numbers Of Bits ; Levels of abstraction ; Loading effects ; Low Power ; Pipeline ADCs ; Power supply ; Scaling factors ; Series capacitors ; Signal to noise ; Tail currents ; Transistor size ; Capacitors ; CMOS integrated circuits ; Digital circuits ; Low power electronics ; Operational amplifiers ; Signal to noise ratio ; Analog to digital conversion
  8. Source: 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 212-215 ; 9781457718458 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6122251