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An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators

Sadrosadati, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1109/ISLPED.2015.7273522
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2015
  4. Abstract:
  5. Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss
  6. Keywords:
  7. Pipelines ; Communication channels (information theory) ; Electric power utilization ; Embedded systems ; Fluidized bed combustion ; Hand held computers ; Low power electronics ; Reconfigurable hardware ; Routers ; Switches ; Switching networks ; VLSI circuits ; Voltage control ; Voltage scaling ; Voltage stabilizing circuits ; Base-line architecture ; Chip Multiprocessor ; Delays ; Network-on-chip(NoC) ; Ports (Computers) ; Power demands ; Resource management ; Total power consumption
  8. Source: Proceedings of the International Symposium on Low Power Electronics and Design, 22 July 2015 through 24 July 2015 ; Volume 2015-September , July , 2015 , Pages 249-254 ; 15334678 (ISSN) ; 9781467380096 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7273522