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Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier

Ebrahimi, A ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/SM2ACD.2010.5672341
  3. Publisher: 2010
  4. Abstract:
  5. In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD
  6. Keywords:
  7. Analog multiplier ; High-bandwidth low power ; Low voltage ; Analog multipliers ; CMOS analog multipliers ; CMOS processs ; Four-quadrant ; High bandwidth ; Low Power ; Low voltages ; Low-voltage ; Simulation result ; Bandwidth ; CMOS integrated circuits ; Frequency multiplying circuits ; Integrated circuit manufacture ; Numerical methods ; Multiplying circuits
  8. Source: 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010, Gammarth ; 2010 ; 9781424468164 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5672341